Storage capacity of an IC memory is increasing more and more, and accordingly an increased IC chip area and formation of patterns at high density are required. As a result, there is an increased possibility that a lowering of the yield of IC memories caused by a very minute defect occurs. In order to prevent the yield of IC memories from being lowered, various failure relieving procedures or processes have been taken wherein a failure or defect element is replaced by a substitute or alternative element.
FIG. 12 generally shows an entire circuit arrangement of a prior conventional memory testing apparatus, and FIG. 13 is an illustration of the inside of an IC memory for explaining an analysis method for failure relief. As shown in FIG. 13, an IC memory includes a main element 17 which is a main storage portion, and four substitute elements 18, 19, 20 and 21 disposed around the main element 17 (in this example, at the lower side and the right side of the main element). The main element 17 has, in this example, the total of 64 storage elements in the form of a matrix of 8 rows.times.8 columns. As shown in the figure, rows are denoted by A, B, C, . . . , H, respectively, and columns are denoted by a, b, c, . . . , h, respectively, for brief explanation. Each of intersecting points or areas Aa, Ab, Ac, . . . , Hh of rows and columns of the main element 17 forms a unit element which is a unit storage element of the IC memory.
The substitute elements 18, 19, 20 and 21 are previously provided in the IC chip for a failure relief and each substitute element comprises a plurality of unit storage elements. In this example, four substitute elements are shown. However, the number of substitute elements and the disposed locations in the IC chip may be arbitrarily selected as the case may be.
Assuming that the IC memory shown in FIG. 13 was tested by a memory testing apparatus shown in FIG. 14 to be described later, and as a result, failures or defects were found in, for example, four unit elements Bb, Be, Df and Fe as shown in FIG. 13 by oblique lines, the row B including the failure unit elements Bb and Be, the column f including the failure unit element Df, and the row F including the failure unit element Fe are removed from the main element 17 so that no failure unit element exists in the main element 17.
Then, the substitute element 18 is substituted for the row B, the substitute element 19 is substituted for the row F, and the substitute element 20 is substituted for the column f. In such a way, by replacing a row or rows and/or a column or columns each including one or more failure unit elements by such substitute elements, the IC memory can be relieved such that all of the addresses thereof can be used even if the IC memory has one or more failure unit elements in the main element 17 thereof.
As described above, in order to relieve an IC memory of a failure element or elements, "information for indicating at which address or addresses a failure unit element or elements exist" which is called a failure map is necessary, and hence, as shown in FIG. 12, a memory testing apparatus having a failure analysis memory (failure memory) 16 for storing therein failure information (data) is used.
This memory testing apparatus comprises a timing generator (TMG GEN) 22, a pattern generator (PTN GEN) 23 and a waveform shaping device (WAVE SHAPE) 24 whereby a predetermined test pattern signal is generated and is applied to a memory under test (IC memory under test) MUT to write predetermined data in the memory under test MUT (hereinafter referred to as MUT). The data written in the MUT are read out therefrom later to supply to a logical comparator (LG COMPA) 14 as a response output signal.
The pattern generator 23 supplies a test pattern signal to an MUT via the waveform shaping device 24 and also supplies an expected value pattern signal (EXP SIG) directly to the logical comparator 14. Further, the pattern generator 23 supplies an address signal (ADR SIG) to the failure analysis memory (FAIL MEM) 16, the address signal specifying the same address as that of an address signal added to both the test pattern signal and the expected value pattern signal.
The logical comparator 14 compares a response output signal read out from an MUT with an expected value pattern signal outputted from the pattern generator 23 and detects as to whether there is an anti-coincidence or mismatch between both signals. That is, when the response output signal does not coincide with the expected value pattern signal, the logical comparator 14 writes in the failure analysis memory 16 a failure signal or data (FAIL SIG) indicating a location of a failure cell (unit element) in the main element 17 of the MUT. The address of the failure analysis memory 16 into which the failure data is written is the same address as the MUT address at which the anti-coincidence has occurred, and the address signal specifying that MUT address is supplied directly to the failure analysis memory 16 from the pattern generator 23, as mentioned above.
The failure analysis memory 16 is provided with a memory having at least the same storage capacity as that of the MUT and the memory is initialized before starting a test. For example, the memory of the failure analysis memory 16 is initialized by writing logical "0s" in all of the addresses thereof. When a failure signal is generated from the logical comparator 14 during a test of an MUT, a mark is written in an address in the memory of the failure analysis memory 16 specified by the above address signal. That is, for example, a logical "1" is written in that address.
In such a way, failure address information of an MUT specifying the addresses of the MUT associated with the failures which occurred during a series of tests is stored in the failure analysis memory 16. The failure data stored in the failure analysis memory 16 are read out therefrom after all of the tests for an MUT are completed. When such failure data are utilized for relieving an MUT of its failure memory element for instance, a failure map is created, which is read out into an arithmetic and logic (hereinafter referred to as arithmetic) or computing part (ALU) 15 to determine a row or rows and/or a column or columns to be relieved.
On the other hand, in a usually utilized testing method such as a marching method or a galloping method or the like, since a plurality of reading tests are performed on the same address of an MUT in a series of tests, a plurality of failure signals may be generated with respect to the same address signal. However, regarding the failure of the same address, a plurality of marks are repeatedly written in the same address one over another so that only information required for the failure relief can be stored.
As described above, the failure analysis memory 16 has at least the same storage capacity as that of an MUT. Whenever a failure signal is generated, a logical "1" is written in the same address location of the failure analysis memory 16 as that of the unit element which has generated the failure signal. Therefore, the failure analysis memory 16 must have at least the same storage capacity as that of an MUT as well as operate at the same operating rate or speed as that of the MUT. For that reason, a conventional failure analysis memory has been constructed by using memory elements called static RAM (SRAM) which can operate at high operating rate. However, since an SRAM is expensive and in addition, an SRAM having large storage capacity cannot be produced, there is a problem that a failure analysis memory having a large storage capacity must be constituted by using a large number of SRAMs.
Consequently, an attempt for using a dynamic RAM (DRAM) which operates at low operating rate or speed, but is inexpensive has been made to construct a failure analysis memory. FIG. 14 shows a circuit construction of a failure analysis memory contemplated in case a DRAM is used.
A method can be contemplated wherein a switching circuit MP and a plurality of memory banks BK#1, BK#2, BK#3, . . . , BK#N are provided in a failure analysis memory 16, and each time a failure signal (failure data) is generated, the switching circuit MP switches the memory banks BK#1-BK#N from one memory bank to next succeeding memory bank to supply the failure signal to the one memory bank thereby distributing the failure data into the plurality of memory banks BK#1, BK#2, BK#3, . . . , BK#N in regular sequence to store therein. This method is generally called an interleave method. By employing this interleave structure, the memory banks BK#1-BK#N can be used each of which operates at an operating rate or speed which is 1/N of that of an MUT.
In case the interleave structure shown in FIG. 14 is employed, an address signal having an address at which a failure signal is generated and the failure signal are randomly supplied to each of the memory banks BK#1-BK#N, and therefore, each of the memory banks BK#1-BK#N requires the same memory capacity as that of an MUT. As a result, when an interleave structure of N phases is arranged, each memory bank must have the memory capacity of N times larger than that of an MUT. Accordingly, there is a shortcoming that the amount of usage of memory elements is increased in proportion to the number of phases N of interleave structure.
In addition, when a failure map which is the information necessary for a relief operation is read out of the failure analysis memory 16 to the computing part 15, in order to obtain the information required to determine whether a relief is necessary or not, the data the number of which is equal to that of all of unit elements constituting an MUT must be read out of the failure analysis memory 16. A long time is necessary for this operation. Consequently, there is a disadvantage that it takes a long time to determine whether a relief is necessary or not, resulting in worse in operation or work efficiency.